1. Field of the Invention
The present invention relates to a semiconductor memory device having a bit line precharge operation, and more particularly to a semiconductor memory device having a precharge operation which is intended for high-speed operation.
2. Description of Related Art
With the recent progress of computer technology which accomplishes animation pictures and other innovative functions, there are intense demands of the larger storage capacity and higher operating speed of semiconductor memory devices such as DRAM (dynamic random access memory). Other requirements which owe to the progress of process technology include the lower power voltage operation and lower power consumption for prevailing portable electronic appliances.
In regard to the data transaction with memory cells which takes place through bit lines, particularly in the case of data readout, a pair of bit lines are laid on both sides of a sense amplifier which implements the differential amplification for the complementary signals of data which is read out of a memory cell. After a data access, the bit line pair need to have the precharge operation for resetting their voltage preparatory to the next data access. The cycle time of data input/output is determined from the sum of the time of data access operation and the time of bit line precharge operation. Accordingly, for speeding up data access, it is crucial to speed up the bit line precharge operation.
FIG. 1 shows the bit line precharge circuit of the conventional semiconductor memory device. In the figure, memory cell Cell-0 and Cell-1 (these are memory cells of DRAM) represent numerous memory cells which are connected between a bit line pair /BL and BL. The bit line pair /BL-BL are further connected to a sense amplifier Samp and a precharge circuit Pre.
The precharge circuit Pre is made up of a transistor TN101 which shorts the bit line pair /BL-BL, and transistors TN102 and TN103 which hold the voltage of the shorted bit line pair /BL-BL at a precharge voltage VPR. These transistors TN101-TN103 are controlled by a precharge signal PREZ which is produced by a precharge signal generation circuit PreC, which is controlled by a data cycle start signal ACTV and precharge cycle start signal PRE provided by a control circuit Cnt.
In order to speed up the precharge operation to meet trends toward the larger storage capacity and lower power voltage operation, the precharge signal PREZ has been devised to gain its driving power. Specifically, the precharge signal generation circuit PreC is configured with high-power transistors so as to match with the total gate capacitance of many sets of transistors TN101-TN103 within the chip, or it is supplied with a higher voltage VPP so as to deal with an increased load resulting from a larger number of transistors TN101-TN103 to drive and a degraded driving power due to the lower power voltage.
However, the demand of the larger storage capacity and higher operating speed is ever growing, which is backed by the progress of low voltage design, and therefore the above-mentioned conventional control circuit increases in its scale on the chip and in its power consumption, while it is still deficient in high-speed performance, as will be described in detail later.
In the case of an increased storage capacity as shown in FIG. 2, the precharge circuits Pre in connection with the precharge signal (PREZ) line have an increased number of sets of transistors TN101-TN103, and the resistance of the PREZ line and the gate capacitance of the transistors TN101-TN103 create CR delays of individual bit line pairs. The CR delay cumulates at each crossing of bit line pair and reaches the maximum value at the farthest bit line pair, and the precharge operation of the memory device as the whole completes only at the end of the latest operation for the farthest bit line pair. The CR time constant which is a key factor of speed-up is determined by the line resistance and gate capacitance, which is beyond the enhanced driving power of the precharge signal generation circuit PreC.
For coping with an increased load capacitance for the precharge signal PREZ due to the larger storage capacity, it is necessary to use larger transistors in the precharge signal generation circuit PreC thereby to gain the driving power of the precharge signal PREZ, however, it adversely results in an increased area of the circuit PreC on the chip against the intention of the higher circuit integration.
The enhancement of output power of the precharge signal generation circuit PreC and the addition or enhancement of power of the voltage step-up circuit for the high-VPP drive of the precharge signal PREZ increase the power consumption against the intention of the lower power voltage.
Due to the progress of process technology and the popularization of portable electronic appliances, in transistor technology, low power design of power voltage has made greater progress than that of threshold voltage has made. As a result, operational margin of transistors against the power voltage VDD tends to reduce. On this account, in order to read data out of memory cells correctly, with the bit line pair /BL-BL being precharged by the conventional precharge circuit Pre, it becomes necessary to short the bit line pair /BL-BL thoroughly, which takes a longer precharge time before proceeding to the next data access operation against the intention of the higher-speed operation.
This affair will be explained more specifically with reference to FIG. 3. The precharge signal PREZ rises to the high level, causing the transistors TN101-TN103 to become conductive, and the precharge operation begins. In this state, the transistors TN101-TN103 have different back bias levels and therefore have different driving power.
Assuming that the bit line BL has a voltage of VDD, the bit line /BL has a voltage of 0 V and the precharge voltage VPR is VDD/2, there is the following bias voltage relation among the transistors at time point t0.
TN101: VGS=VDD, VDS=VDD, VBS=0 PA1 TN102: VGS=VDD, VDS=VDD/2, VBS=0 PA1 TN103: VGS=VDD/2, VDS=VDD/2, VBS=VDD/2 PA1 TN101: VGS=VDD/2, VDS=.alpha.VBS=VDD/2 PA1 TN102: VGS=VDD/2, VDS=0, VBS=VDD/2 PA1 TN103: VGS=VDD/2, VDS=.alpha.VBS=VDD/2 PA1 TN101: VGS=VDD-(VDD/2+.alpha.2), VDS=0, VBS=VDD/2+.alpha.2 PA1 TN102: VGS=VDD/2, VDS=.alpha.2, VBS=VDD/2 PA1 TN103: VGS=VDD/2, VDS=.alpha.2, VBS=VDD/2
At a time point between t0 and t1, the transistor TN101 becomes conductive deepest among the transistors due to the bias relation to begin to short the bit line pair /BL-BL. The transistor TN102 becomes conductive deeply next to short the bit line /BL (0 V) to the precharge voltage VPR (i.e., VDD/2), and the transistor TN103 shorts the bit line BL (VDD) to the precharge voltage VPR (i.e., VDD/2) weaker than the transistor TN102. At time point t1, the bit line BL has VPR+.alpha. and the /BL has VPR, with these transistors having the following bias voltage conditions.
At time point t1, the transistors TN101 and TN103 conduct currents to short the bit lines, whereas the transistor TN102 having VDS=0 does not conduct a current. At time point between t1 and t2, the transistor TN101 keeps to short the bit line pair /BL-BL, which are then pulled to a voltage level of VDD/2+.alpha.2. At time point t2, the bias voltage conditions become as follows.
Finally, the bit lines /BL and BL will have their voltage level approaching to VPR (i.e., VDD/2).
The above-mentioned .alpha. is a constant determined from the circuit parameters, and it has a small value when the transistors TN101-TN103 have a sufficient driving power for the precharge operation, making the voltage difference of the bit lines /BL and BL at time point t1 to be negligible for the sense amplifier SAmp. However, in terms of progress in low power voltage design for transistors, low voltage design level of threshold voltage has not kept pace up with that of power voltage, wherein threshold voltage seems to rise relatively higher compared with the low power voltage. Therefore, when the transistors TN101-TN103 have little operational margin, which is due to the relatively rising threshold voltage, the a has a significant value, by which the sense amplifier SAmp cannot operate normally any longer at time point t1, and the need of elongated precharge time will retard the speed-up of data access.